1. Field
This disclosure relates generally to analog-to-digital converters, and more specifically, to a full first-order noise shaping successive approximation register analog-to-digital converter.
2. Background
Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used in various applications that may require low power and area efficient ADCs. Recently, SAR ADC has acquired more attention due to improved capacitor matching and availability of metal capacitors with very small unit sizes (e.g., sub-femto-Farad capacitors are available in modern complementary metal oxide semiconductor (CMOS) technologies).
FIG. 1 is a functional block diagram of a SAR ADC 100 in which an analog input voltage (Vin) is sampled by a switch 110 when the clock is high and the conversion is started when the clock goes low and the input voltage is disconnected. Initially, a binary search is performed by a comparator 130 and a SAR logic unit 140 to find a digital output. To resolve n+1 bits, n digital-to-analog converter (DAC) operations are performed by a DAC 120. Thus, the digital output (Dout) is a digital representation of the analog input voltage including any quantization noise (Q).
If one additional DAC operation is performed (i.e., n+1 DAC operations), the final residue stored on the capacitor array of the DAC is equal to the quantization noise. Thus, in a SAR architecture, which uses the capacitor array as the DAC, the quantization noise of each conversion can be extracted at the end of the conversion from the capacitor array analog residue remaining from the SAR operation.
FIG. 2 is a functional block diagram of a SAR ADC 200 including one implementation of a noise shaping. In FIG. 2, an analog input voltage (Vin) is sampled by a switch 210 when the clock is high and the conversion is started when the clock goes low and the input voltage is disconnected. A binary search is performed by a comparator 230 and a SAR logic unit 240 to find a digital output. In FIG. 2, n+1 DAC operations are performed by a DAC 220. A quantization noise is left on the capacitor array of the DAC 220 after the (n+1)th DAC operation. The noise shaping is performed by offsetting a reference voltage (Vref) by the quantization noise of the previous conversion (i.e., the residue left on the capacitor array). The noise shaping is in the form of
  1      1    +          z              -        1            as shown below in Equations (1), (2), and (3):
                                                        D              out                        ⁡                          (              k              )                                =                                                    V                in                            ⁡                              (                k                )                                      +                          Q              ⁡                              (                k                )                                      -                                          V                res                            ⁡                              (                                  k                  -                  1                                )                                                    ,        where                            (        1        )                                                                    V              res                        ⁡                          (              k              )                                =                                                    D                out                            ⁡                              (                k                )                                      -                                          V                in                            ⁡                              (                k                )                                                    ,                            (        2        )                                                      D            out                    ⁡                      (            z            )                          =                                            V              in                        ⁡                          (              z              )                                +                                    1                              1                +                                  z                                      -                    1                                                                        *                                          Q                ⁡                                  (                  z                  )                                            .                                                          (        3        )            However, this provides only 6-dB improvement at DC and may require more complex hardware as compared to adding one extra bit (which also provides 6-dB improvement).